Conventional time-slot interchange (TSI) switches utilize both data and connection memories to control routing of a plurality of input and output data streams. As illustrated by FIGS. 1 and 2A, a conventional TSI switch may be operated under microprocessor control and each input data stream (RX) and output data stream (TX) may be configured as a serial stream of multi-bit (e.g., 8-bit) channels that are partitioned into fixed-duration frames. These multi-bit channels may be multiplexed in time and/or space between any one of a plurality of the input data streams and output data streams, as illustrated by FIG. 3. Conventional TSI switches are disclosed by U.S. Pat. Nos. 4,510,597 and 6,259,703 to Mitel Corporation. In sub-rate switching applications, 1-bit, 2-bit and 4-bit channels may be provided.
A TSI switch typically enables a user to perform manual microprocessor-based programming of individual connection memory entries with data memory addresses and switching mode data when the switch is actively processing serial data streams. Such manual operations may be time consuming and require substantial microprocessor bandwidth. The performance of conventional test and debugging operations on downstream elements in a communication path may also be complicated by the presence of a TSI switch in the path. In particular, to enable test and debugging operations to be performed on downstream elements, it may be necessary to set the TSI switch into a one-to-one RX-to-TX routing mode with constant delay. Unfortunately, this routing mode inherently results in multiple frames of delay through the TSI switch during debugging.
Conventional TSI switches may also provide global or per-channel high-impedance (high-Z) output control associated with the output data streams (TX). For example, output enable (OE) bits within a connection memory (CM) of the TSI switch may be set to provide per-channel high-impedance output control. Global high-impedance output control of all output data streams may be provided by an output drive enable (ODE) pin of the TSI switch. This pin may operate in conjunction with an output standby (OSB) bit within a control register (CR) in the TSI switch. These conventional per-channel and global high-Z control features are more fully illustrated below in Table 1.
TABLE 1TX StreamOE bit in CMODE pinOSB bit in CROutput Status0Don't CareDon't CarePer-ChannelHigh-Z100Global High-Z101TX Enabled110TX Enabled111TX Enabled
Notwithstanding these TSI switches, there continues to be a need for switches that can be programmed and operated more efficiently and facilitate more efficient testing and debugging operations.